Vertical transistors and buried conductive lines facilitate dense and compact arrangements of logic circuits and memory cells. A vertical transistor includes a buried source/drain region that is connected to a buried conductive. A gate electrode, which is configured to control a current flow through the vertical transistor, is disposed along a body region between the buried source/drain region and a top source/drain region that may be formed at or near a substrate surface. The gate electrode controls the formation of an inversion layer of minority charge carriers (conductive channel) in the body region in dependence on a voltage supplied to the gate electrode. In the conductive channel a current flows between the two source/drain regions. The body region of a conventional vertical transistor is connected to a bulk portion of the substrate in which it is formed in order to avoid charge carrier accumulation in the body region and floating body effects resulting thereof.
The amount of a capacitive coupling between the gate electrode and the buried conductive structure on the one hand and the resistance of the body region in the transistor on-state on the other hand contribute to the transistor characteristics. A need exists for vertical transistors with enhanced transistor characteristics.